1.Which of the following statements is true?

 

the MMU contains the table that lists physical addresses and their corresponding logical addresses

 

there can be no more than three MIPS instructions that are pipelined in a single CPU clock cycle

 

None of the other answers are true

 

virtual memory is the fastest component of the memory hierarchy

 

the cache contains the Control Unit of the CPU

 

 

2.For this MIPS assembly language program:

# Add the numbers in an array

 

.data

sum: .word

i: .word

a: .word 7,8,9,10,8

 

.text
main:
add $t0,$zero,$zero
add $t5,$zero,$zero # i in $t5 = 0
add $t4,$zero,$zero # sum in $t4 = 0

loop:
sll $t1,$t5,2 # convert “i” to word offset
lw $t1,a($t1) # load a[i]
add $t4,$t4,$t1 # sum = sum + a[i];
addi $t5,$t5,1
slti $t1,$t5,5
bne $t1,$t0,loop

sw $t4,sum($zero) # update final sum in memory
sw $t5,i($zero) # update final i in memory

There is a loop being used to perform the addition of all of the array elements in an array of integers.

 

Please provide answers to the following parts of this question.Each answer should be no more than 2 sentences.

 

  1. a) What will the value in $t0 be when the loop ends?

 

  1. b) If the MIPS pipeline has five stages, will the sll $t1,$t5,2 and bne $t1,$t0,loop instructions both be in the pipeline when the loop is executing?

 

  1. c) Are the values associated with the sum and the i labels stored in the cache before the loop begins? Please answer Yes or No.

 

  1. d) Two of the labels from the data segment have the values associated with them stored in the part of the memory hierarchy that exists outside the CPU once the loop ends. Which two labels are these?

 

  1. Which of the following isnot32 bits long in the MIPS architecture?

 

logical address

 

$sp

 

heap memory range of addresses

 

physical address

 

$a0

 

  1. Suppose there was a way to combine the fetch stage and the decode stage of the MIPS Fetch Execution Cycle into a single stage.Also suppose this new single stage could be performed in one clock cycle for all instructions.That would mean the number of stages in the Fetch Execution Cycle would be changed from 5 stages to 4 stages.

 

 

  1. a) Would decreasing the number of Fetch Execution stages increase the speed of an arithmetic assembly language instruction like addi?Answer Yes or No.

 

  1. b) Would decreasing the number of Fetch Execution stages increase the speed of a data movement assembly language instruction like lw?Answer Yes or No.

 

  1. c) Would decreasing the number of Fetch Execution stages increase the speed of a branching assembly language instruction like beq?Answer Yes or No.

 

  1. d) Would decreasing the number of Fetch Execution stages increase the clock speed?Answer Yes or No.

 

  1. e) Would decreasing the number of Fetch Execution stages prevent hazards from occurring? Answer Yes or No.

 

  1. f) Would decreasing the number of Fetch Execution stages increase or decrease the number of instructions that can be pipelined at the same time? Answer Increase or Decrease.

 

  1. When does virtual memory get data and instructions stored in it?

 

when there is not enough available memory in RAM for programs that are running

 

when the MMU cannot determine which physical address corresponds to which logical address

 

when all of the CPU general purpose registers are not being used

 

when all of the CPU general purpose registers are in use, the cache is full, and the stack and the heap/free store are not using all of the memory addresses allocated to them

 

  1. Given the following MIPS assembly language program:

.text

main:
li $t0, 10
li $t1, 0
li $t2, 0

start:
x: slti $t0, $t2, 0
bne $t0, $zero, y
add $t1, $t1, $t2
addi $t2, $t2, 1
j x
y:

Please answer the following questions.Each answer must be no more than 1 sentence long.

 

  1. a) Does this program contain a loop? Please Answer Yes or No.
  2. b) Does this program contain a function call? Please Answer Yes or No.

 

  1. c) How many times is the start label unconditionally branched to by this program?

 

  1. d) In this program is it possible for a data hazard to occur in the pipeline with any instruction that uses the $t0 register? Please Answer Yes or No.

 

  1. e) Will data forwarding be needed in this program? If so, state why. If not, state why not.

 

  1. f) Of the three regions of the memory hierarchy:
  • the registers region
  • the cache region
  • the Main Memory region

 

Which regions are not being accessed with the instructions that occur after the start label?

 

  1. Which IC inside the CPU is used in managing the steps of the Fetch Execution Cycle?

 

$zero register

 

None of the other answers are correct

 

$sp register

 

Control Unit

 

  1. The Main Memory region of the memory hierarchy contains which of the following?

 

RAM only

 

registers and RAM only

 

RAM and virtual memory only

 

virtual memory only

 

cache, RAM, and virtual memory

  1. Which one of these regions of the memory hierarchy is accessed the most frequently when a programs instructions are being executed?

 

virtual memory

 

cache

 

RAM

 

  1. Given the following MIPS assembly language program:

.text
main:
li $s0, 2
li $s1, 1
move $a0, $s0

jal fun # Call function

move $s1,$v0

li $v0, 10
syscall

fun: addi $sp,$sp,-4
sw $s0,0($sp)
addi $sp,$sp,-4
sw $s1,0($sp)

# function logic
li $s0, 3
add $s1,$s0,$a0
addi $s1,$s1,5

# Save the return value in $v0
move $v0,$s1

lw $s1,0($sp)
addi $sp,$sp,4
lw $s0,0($sp)
addi $sp,$sp,4

jr $ra

Please answer the following questions.Each answer must be no more than 1 sentence long.

 

 

  1. a) What is the name of the function being called?

 

  1. b) What is the purpose of the $ra register?

 

  1. c) What is the purpose of the $a0 register?

 

  1. d) At the beginning of the function being called, what are the numeric values placed on the stack?

 

  1. e) What number is being calculated by the function, and is also used as the return value of the function?

 

  1. f) After theli $v0, 10instruction is executed in the main part of the program, which register or registers contain the return value of the function?

 

  1. For this MIPS assembly language code:

 

# Initialize registers

li $t0, 5
li $t1, 3

li $t2, 0

# Main loop body

loop: addi $t1, $t1, 1

add $t2, $t2, $t1

beq $t0, $t1, exit

j loop

exit:

 

 

There is a loop being used to perform several additions.

 

Please provide an answer for each of a), b), c), d), e), and f) below.Each answer must be no more than 1 sentence.

 

  1. a) Loops have their instructions stored in cache so they do not have their instructions loaded into the CPU from Main Memory. Given that, which instructions in the program are going to be in the cache?

 

  1. b) Are there any instructions in the program above that will need to access RAM or virtual memory? Please answer Yes or No.

 

  1. c) What is the only instruction in the program above that uses a memory address of Main Memory which exists outside of the memory addresses used to perform the loop?

 

  1. d) Recall that the memory hierarchy regions are the register region, the cache region, and the Main Memory region. Given that, what is the only instruction in the program above that is a part of the loop and does not need to access the fastest region of the memory hierarchy?

 

  1. e) There are three instructions in the program above that are guaranteed not to load data from the cache, RAM, and virtual memory components of the memory hierarchy. What three instructions are these?